This disclosure relates to communication systems capable of performing tests using cyclic patterns that repeat fixed bit-sequences. This disclosure also relates to data transmitters and data receivers that are suitable to construct the data communication systems.
Pseudo random bit sequence patterns (PRBS patterns), standardized according to the recommendation by International Telecommunication Union, Telecommunication Standardization Sector (ITU-T), are widely utilized for testing communication systems.
FIG. 5 is a schematic drawing that shows an exemplary construction of a conventional communication system capable of performing a test using the PRBS pattern. The communication system 100 shown in FIG. 5 includes a data transmitter 110 and a data receiver 120.
The data transmitter 110 includes a PRBS pattern generating circuit 111 that generates an m-bit parallel PRBS pattern in synchronous with a clock signal CLK. The data transmitter 110 also includes a serializer 112 that converts the parallel PRBS pattern generated by the PRBS pattern generating circuit 111 into serial data SD.
The data receiver 120 includes a clock-data recovery circuit 121, which receives the serial data SD transmitted from the serializer 112, generates a clock signal in synchronous with the received serial data SD, acquire the serial data SD using the generated clock signal, and outputs m-bit parallel data. The data receiver 120 also includes a PRBS pattern generating circuit 122 that generates a PRBS pattern having the construction same as the construction of the PRBS pattern generating circuit 111 in the data transmitter 110. The PRBS pattern generating circuit 122 generates a reference PRBS pattern to be compared with the parallel data output from the clock-data recovery circuit 121.
The data receiver 120 further includes a comparing and checking circuit 123. The comparing and checking circuit 123 compares the parallel data output from the clock-data recovery circuit 121 and the reference PRBS pattern generated by the PRBS pattern generating circuit 122, and checks if the serial data SD transmitted from the transmitter 110 is correctly received by the data receiver 120.
In the communication system 100 thus constructed, a test for checking if the serial data SD transmitted from the data transmitter 110 is correctly received by the data receiver 120 may be performed in the following steps.
(Step 1) The data transmitter 110 converts, using the serializer 112, the parallel PRBS pattern generated by the PRBS pattern generation circuit 111 into serial data SD, and transmits the serial data SD to the data receiver 120.
(Step 2) The data receiver 120 receives the serial data SD transmitted from the data transmitter 120 using the clock-data recovery circuit 121. The clock-data recovery circuit 121 generates parallel data based on the received serial data SD and outputs the generated parallel data to the PRBS pattern generating circuit 122 and to the comparing and checking circuit 123. When the first m bits of the parallel data is input from the clock-data recovery circuit 121, the PRBS pattern generating circuit 122 starts generating reference PRBS pattern using the first m bits as initial values.
(Step 3) The comparing and checking circuit 123 compares the parallel data received from the clock-data recovery circuit 121 with the reference PRBS pattern received from the PRBS pattern generating circuit 122.
(Step 4) When the parallel data does not matches the reference PRBS pattern, the comparing and checking circuit 123 checks that the serial data SD transmitted from the data transmitter is not correctly received by the data receiver 120, and generates a bit-fault determination signal ERR. Thus, a test for checking if the serial data SD transmitted from the data transmitter 110 is correctly received by the data receiver 120 is performed.
US Patent Publications Nos. 2008/0114562 and 2008/0240212 disclose exemplary data communication apparatuses capable of performing the test described above.
FIG. 5 is a schematic drawing that shows an exemplary communication system that utilizes a first communication scheme between the data transmitter and the data receiver. In the first communication scheme, the data transmitter transmits serial data with the clock embedded therein and the data receiver recovers a clock signal in synchronous with the serial data. There is another communication scheme (a second communication scheme) where the serial data and the clock signal are transmitted through separate transmission lines.
FIG. 6 is a schematic drawing that shows an exemplary communication system that utilizes a second communication scheme. The data transmission system 200 shown in FIG. 6 may be used in, for example, a liquid-crystal display panel that includes a data transmitter 210 and a data receiver 220.
The data transmitter 210 includes a low voltage differential signal transmitter (LVDS-Tx) 211. Three sets of parallel data PD1, PD2, PD3, and a clock signal CLK are input to the LVDS-Tx 211. The LVDS-Tx 211 converts these parallel data PD1, PD2, and PD3 into serial data SD1, SD2, and SD3, which are synchronized with the clock signal CLK. The converted serial data SD1, SD2, and SD3 are transmitted to the data receiver 220 together with the clock signal.
The data receiver 220 includes a low voltage differential signal receiver (LVDS-Rx) 221. The serial data SD1, SD2, SD3 and the clock signal from the LVDS-Tx 211 are received by the LVDS-Rx 221. The LVDS-Rx 221 acquires the serial data SD1, SD2, and SD3 using the clock signal CLK, and converts these data into parallel data PD11, PD12, and PD13.
FIG. 7 shows an exemplary timing relationship between the serial data SD1 received by the data receiver 220, and the clock signal CLK. Timing relationships between the serial data SD2 and SD3 and the clock signal CLK are the same as the relationship between the serial data SD1 and the clock signal CLK.
FIG. 7 is a timing chart that shows an exemplary timing relationship between the serial data and the clock signal received by the data receiver shown in FIG. 6. FIG. 7 shows the serial data SD1 and the clock signal CLK received by the data receiver 220. FIG. 7 also shows the parallel data PD11 converted from the serial data acquired by the receiver 220. As shown in FIG. 7, the serial data SD1 may includes a bit stream including bits of . . . A[3], A[2], A[1], A[0], B[6], B[5], B[4], B[3], B[2], B[1], B[0], C[6], C[5], C[4], C[3], C[2], . . . .
The data receiver 220 successively acquires 7 bits in the serial data SD1 in synchronous with each rising edge of the clock signal CLK, and converts the acquired serial data into 7-bit parallel data PD11 in the order of the acquisition.
In the data receiver 220, the relationship between the data and the clock signal is determined in accordance with the application. For example, the data receiver 220 acquires seven consecutive bits of the serial data A[6], . . . , A[0] in synchronous with a clock signal having a rising edge between the bits A[2] and A[1] of the serial data. These bits are converted into 7-bit parallel data A[6:0], where the bit A[6] forms the most significant bit (MSB), and the bit A[0] forms the least significant bit (LSB) of the 7-bit parallel data,
Similarly, the data receiver 220 acquires next seven consecutive bits of the serial data B[6], . . . , B[0] in synchronous with the clock signal having the next rising edge between the bits B[2] and B[1]. The data receiver 220 further acquires following bits of the serial data and converts into a stream of parallel data.
The previously described test using the PRBS pattern may also be performed in data communication systems according to the second communication scheme. FIG. 8 is a schematic drawing that shows an exemplary construction of a data communication system in accordance with the second communication scheme capable of performing a test using the PRBS pattern.
The exemplary data transmission system 300 shown in FIG. 8 includes a data transmitter 310 and a data receiver 320. The data receiver 320 may be a product to be tested, and the data transmitter 310 may be an apparatus for testing the data receiver 320. It is also possible to reverse the relationship between the product and the apparatus for testing.
The data transmitter 310 includes a PRBS pattern generating circuit 311 and a serializer 312. The PRBS pattern generating circuit 311 generates 8-bit parallel PRBS pattern in synchronous with a clock signal CLK. The PRBS pattern generating circuit 311 may generate 8-bit parallel PRBS pattern by dividing a cyclic pattern, which has 7 bits per cycle, at every 8 bits. The serializer 312 converts the 8-bit parallel PRBS pattern generated by the PRBS pattern generating circuit 311 into serial data SD in synchronous with the clock signal CLK and transmits to the data receiver together with the clock signal.
The data receiver 320 includes a de-serializer 321, a PRBS pattern generating circuit 322, and a comparing and checking circuit 323. The de-serializer 321 converts the serial data SD transmitted from the data transmitter 310 into 8-bit parallel data in synchronous with the clock signal CLK. That is, the data receiver 320 receives 8-bit parallel data by using the de-serializer 321. After receiving the first 8 bits of the parallel data (initial values) from the de-serializer 321, the PRBS pattern generating circuit 322 starts generating PRBS pattern that follows the initial values, which is used as a reference pattern.
The comparing and checking circuit 323 compares the parallel data output from the de-serializer 321 and the reference PRBS pattern generated by the PRBS pattern generating circuit 322. Thereby, the comparing and checking circuit 323 attempts to check whether the serial data SD transmitted from the data transmitter 310 is correctly received without any error by the data receiver 320.
However, this inventor discovered that the communication system 300 has a problem that it is difficult to detect incorrect receipt of the data due to a “bit-shift”, which is a type of errors that might occur in the received parallel data stream.